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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost Subscriber Line Interface Circuit (SLIC)
Features
s s s s s s s s s s s s s s
Description
The L8575 is a dual-resistive, low-cost subscriber line interface circuit (SLIC) that is optimized to meet both ITU-T recommendations and LSSGR requirements for 600 /900 resistive and complex impedance termination applications. It interfaces the lowvoltage circuits on an analog line card to the Tip and Ring of two subscriber loops. The L8575 does not supply dc current to the subscriber loops--external resistors are used for this purpose. The device is built using a 90 V complementary bipolar (CBIC) process and is available in a 44-pin PLCC package.
Two channels in a single package Serial data interface Per-channel powerdown Low standby power (65 mW per channel) Integrated protection No external protection device required Battery noise cancellation Switchhook detector Ring-trip detector Switchhook and ring-trip detector self-test Fault detector Zero ring voltage cross detection Three relay drivers per channel 44-pin, surface-mount, plastic package (PLCC)
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Table of Contents
Contents Page
Features .................................................................................................................................................................. 1 Description ...............................................................................................................................................................1 Preliminary Pin Information ..................................................................................................................................... 5 Absolute Maximum Ratings (@ TA = 25 C) ............................................................................................................ 8 Electrical Characteristics ......................................................................................................................................... 9 Relay Drivers ..................................................................................................................................................... 11 Transmission...................................................................................................................................................... 13 Serial Interface and Logic .................................................................................................................................. 14 Applications ........................................................................................................................................................... 16 General .............................................................................................................................................................. 16 Resistor Module................................................................................................................................................. 16 Protection .......................................................................................................................................................... 18 Tip/Ring Drivers ................................................................................................................................................. 20 Receive Interface............................................................................................................................................... 20 Transmit Interface .............................................................................................................................................. 20 Battery Noise Cancellation ................................................................................................................................ 20 On-Hook Transmission....................................................................................................................................... 21 Self-Test............................................................................................................................................................. 21 Serial Data Interface .......................................................................................................................................... 21 Operating States.................................................................................................................................................... 24 Active State........................................................................................................................................................ 24 Test State........................................................................................................................................................... 24 Powerdown State with Relay Driver RDD Operated .......................................................................................... 24 Powerdown State............................................................................................................................................... 24 Ringing State (D2 = 1) ....................................................................................................................................... 24 Supervision............................................................................................................................................................ 25 Off-Hook Detection ............................................................................................................................................ 25 Ring-Trip Threshold ........................................................................................................................................... 25 Ring-Trip Requirements......................................................................................................................................25 Fault Detection................................................................................................................................................... 26 Zero Voltage Current Cross ............................................................................................................................... 26 Relay Drivers ..................................................................................................................................................... 26 dc Characteristics .................................................................................................................................................. 27 I/V Characteristics ............................................................................................................................................. 27 Loop Length....................................................................................................................................................... 27 ac Design............................................................................................................................................................... 28 Codec Features and Selection Summary.......................................................................................................... 28 Design Equations .............................................................................................................................................. 29 Application Diagram ..............................................................................................................................................33 Outline Diagram..................................................................................................................................................... 35 44-Pin PLCC...................................................................................................................................................... 35 Ordering Information ..............................................................................................................................................36
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Table of Contents (continued)
Tables Page
Table 1. Pin Descriptions .......................................................................................................................................... 5 Table 2. Operating Conditions and Powering ............................................................................................................9 Table 3. Battery Feed, Switchhook Detectors (LCA and LCB), and Fault Detectors (FLTA and FLTB)................... 10 Table 4. Ring-Trip Detectors (RTA, RTB, RZA, and RZB) ....................................................................................... 10 Table 5. Relay Drivers (RDRA, RDTA, RDRB, RDTB, RDDA, and RDDB)............................................................. 11 Table 6. Analog Signal Pins .................................................................................................................................... 11 Table 7. Transmission Characteristics..................................................................................................................... 13 Table 8. Logic Inputs (CLK, EN, and DI) and Outputs (DO).................................................................................... 14 Table 9. Timing Requirements for CLK, EN, DI, and DO ........................................................................................ 14 Table 10. MMC* A31A8575AA Thick Film Resistor Module.................................................................................... 17 Table 11. Total Module Power Dissipation .............................................................................................................. 19 Table 12. Truth Table for EN and CLK ..................................................................................................................... 22 Table 13. Output DATA Bit Definition .......................................................................................................................22 Table 14. Input DATA Bit Definition.......................................................................................................................... 23 Table 15. Truth Table for D1 and D0........................................................................................................................ 24 Table 16. External Components Required ...............................................................................................................33
Figures
Page
Figure 1. Functional Diagram ....................................................................................................................................4 Figure 2. 44-Pin PLCC Pinout .................................................................................................................................. 5 Figure 3. Power Supply Rejection vs. Frequency Diagram ..................................................................................... 15 Figure 4. L8575 SLIC Resistor Module................................................................................................................... 17 Figure 5. L8575 SLIC Dual-Resistive Matching Requirements .............................................................................. 18 Figure 6. Self-Test Mode Circuit ............................................................................................................................. 21 Figure 7. Timing Requirements for CLK, EN, DI, and DO ...................................................................................... 22 Figure 8. Logic Diagram (Positive Logic; Flip-Flops Clocked on High-to-Low Transition) ....................................... 23 Figure 9. Ring-Trip Threshold ................................................................................................................................. 25 Figure 10. Ring-Trip Circuits ...................................................................................................................................25 Figure 11. L8575 SLIC I/V Template .......................................................................................................................27 Figure 12. Equivalent Complex Terminations ..........................................................................................................29 Figure 13. Initial ac Interface for Complex Termination Between L8575 SLIC and T7504 Codec ..........................30 Figure 14. Revised ac Interface CT and CR Combined into a Single Capacitor CS..................................................31 Figure 15. Addition of Resistor RSC from XMT to IRP .............................................................................................32 Figure 16. Typical Application Diagram with Blocking Capacitors (CB) Included ....................................................34
* MMC is a registered trademark of Microelectronic Modules Corporation.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Description (continued)
RDDA RDRA RDRA DGND VDDD DI DO CLK EN RDTB RDRB RDDB
RELAY DRIVER
RELAY DRIVER
RELAY DRIVER +5D SERIAL DATA INTERFACE, LATCHES, AND LOGIC
RELAY DRIVER
RELAY DRIVER
RELAY DRIVER
NFLTA VBAT SWITCHHOOK AND FAULT DETECTORS A NLCA CONTROL DETECTORS CFLTA
TSA RSA
- AXA + TIP CURRENT SOURCE A
XMTA TSTA PDA
PTA RTPA RTNA RECEIVE INTERFACE AND BATTERY NOISE CANCELLATION A VRNA IRPA CBNA RGBNA PRA NPLTB NLCB RING CURRENT SOURCE A CFLTB
RING-TRIP DETECTOR A
NRTA
VBAT
VBAT
SWITCHHOOK AND FAULT DETECTORS B
VBAT
TSB RSB
- AXB + TIP CURRENT SOURCE B TSTB PDB XMTB
PTB RTPB RTNB PRB +5 A VBAT VBAT VDDA AGND VBAT RING CURRENT SOURCE B RECEIVE INTERFACE AND BATTERY NOISE CANCELLATION B VRNB IRPB CBNB RGBNB
RING-TRIP DETECTOR B
NRTB
VBAT
12-3304(F).ar1
Figure 1. Functional Diagram
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Preliminary Pin Information
DGND CFLTB VDDD DGND 40 39 38 37 36 35 RDDA RDRA RDTA RTPA RTNA XMTA TSA RSA RGBNA VRNA IRPA 34 33 32 31 30 29 18 PTB 19 PRB 20 AGND 21 VBAT 22 CBNB 23 VDDA 24 CBNA 25 VBAT 26 AGND 27 PRA 28 PTA CFLTA 42 VDDD 41
CLK 44
DO
NC
6 RDDB RDRB RDTB RTPB RTNB XMTB TSB RSB RGBNB VRNB IRPB 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
43
L8575
EN
DI
12-3364(F)
Figure 2. 44-Pin PLCC Pinout Table 1. Pin Descriptions Pin Symbol Type NC -- 1 2 DO O 3 4 5 6 7 8 9 10 DI CFLTB VDDD DGND RDDB RDRB RDTB RTPB I I/O -- -- O O O I Name/Function No Connect. Unused pin (no internal connection). Serial Data Output. Data in the internal 8-bit serial shift register is shifted out on this logic output with the clock signal on pin CLK. Serial Data Input. Data on this logic input is shifted into the 8-bit serial shift register with the clock signal on pin CLK. Fault Filter (Channel B). Connect a 0.1 F capacitor from CFLTB to AGND. This capacitor filters Tip/Ring transients from the channel B fault detector. 5 V Digital dc Supply. 5 V supply for logic and relay driver flyback diodes. Digital Ground. Ground for channel B relay drivers. Disconnect Relay Driver (Channel B). This output drives the external relay. Ringing Relay Driver (Channel B). This output drives an external ringing relay. Test Relay Driver (Channel B). This output drives an external test relay. Ring-Trip Positive (Channel B). Positive sense input for the ring-trip detector.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Preliminary Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin Symbol Type I 11 RTNB 12 XMTB O 13 TSB I Name/Function Ring-Trip Negative (Channel B). Negative sense input for the ring-trip detector. Transmit Signal Output (Channel B). Channel B transmit amplifier output. Tip Sense (Channel B). Negative input of channel B transmit op amp. Connect one highvalue resistor between TSB and the Tip of loop B and another high-value resistor between TSB and XMTB. Ring Sense (Channel B). Positive input of channel B transmit op amp. Connect one highvalue resistor between RSB and the Ring of loop B and another high-value resistor between RSB and AGND. Battery Noise Gain Resistor (Channel B). The current flowing out of PRB is 50 times the current flowing into RGBNB. Connect a resistor from RGBNB to AGND to set the gain of the channel B battery noise cancellation circuit. Receive Voltage Negative Input (Channel B). The differential current flowing from PTB to PRB is -200 times the voltage applied to VRNB, divided by the impedance connected between IRPB and AGND. Receive Current Positive Input (Channel B). The differential current flowing from PTB to PRB is 200 times the current flowing into IRPB. Protected Tip (Channel B). Output of the Tip current drive amplifier B. Connect PTB to the Tip of loop B through an overvoltage protection resistor (1.4 k minimum). Protected Ring (Channel B). Output of the Ring current drive amplifier B. Connect PRB to the Ring of loop B through an overvoltage protection resistor (1.4 k minimum). Analog Signal Ground. Signal ground for channel B. Office Battery Supply. Negative office battery supply for channel B. Battery Noise Capacitor (Channel B). The current flowing out of PRB is -50 times the voltage applied to CBNB, divided by the impedance connected between RGBNB and AGND. Couple VBAT to CBNB through a high-pass filter to eliminate battery noise from the Tip/Ring of channel B. 5 V Analog dc Supply. Battery Noise Capacitor (Channel A). The current flowing out of PRA is -50 times the voltage applied to CBNA, divided by the impedance connected between RGBNA and AGND. Couple VBAT to CBNA through a high-pass filter to eliminate battery noise from the Tip/Ring of channel A. Office Battery Supply. Negative office battery supply for channel A. Analog Signal Ground. Signal ground for channel A. Protected Ring (Channel A). Output of the Ring current drive amplifier A. Connect PRA to the Ring of loop A through an overvoltage protection resistor (1.4 k minimum). Protected Tip (Channel A). Output of the Tip current drive amplifier A. Connect PTA to the Tip of loop A through an overvoltage protection resistor (1.4 k minimum). Receive Current Positive Input (Channel A). The differential current flowing from PTA to PRA is 200 times the current flowing into IRPA. Receive Voltage Negative Input (Channel A). The differential current flowing from PTA to PRA is -200 times the voltage applied to VRNA, divided by the impedance connected between IRPA and AGND.
14
RSB
I
15 RGBNB
I
16
VRNB
I
17 18 19 20 21 22
IRPB PTB PRB AGND VBAT CBNB
I O O -- -- I
23 24
VDDA CBNA
-- I
25 26 27 28 29 30
VBAT AGND PRA PTA IRPA VRNA
-- -- O O I I
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Preliminary Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 31 Symbol RGBNA Type I Name/Function Battery Noise Gain Resistor (Channel A). The current flowing out of PRA is 50 times the current flowing into RGBNA. Connect a resistor from RGBNA to AGND to set the gain of the channel A battery noise cancellation circuit. Ring Sense (Channel A). Positive input of channel A transmit op amp. Connect one high-value resistor between RSA and the Ring of loop A and another high-value resistor between RSA and AGND. Tip Sense (Channel A). Negative input of channel A transmit op amp. Connect one high-value resistor between TSA and the Tip of loop A and another high-value resistor between TSA and XMTA. Transmit Signal Output (Channel A). Channel A transmit amplifier output. Ring-Trip Negative (Channel A). Negative sense input for the ring-trip detector. Ring-Trip Positive (Channel A). Positive sense input for the ring-trip detector. Test Relay Driver (Channel A). This output drives an external test relay. Ringing Relay Driver (Channel A). This output drives the external ringing relay. Disconnect Relay Driver (Channel A). This output drives an external relay. Digital Ground. Ground for channel A relay drivers. 5 V Digital dc Supply. 5 V supply for logic and relay driver flyback diodes. Fault Filter (Channel A). Connect a 0.1 F capacitor from CFLTA to AGND. This capacitor filters Tip/Ring transients from the channel A fault detector. Enable. A high-to-low transition on this logic input latches the data in the 8-bit serial shift register into the output latches. The logic level of EN also controls which data is shifted into the 8-bit serial shift register (refer to CLK pin description). Clock. When the enable input (EN) is high, a low-to-high transition on this logic input shifts data at the data input pin (DI) into the 8-bit serial shift register. When the enable input (EN) is low, a low-to-high transition latches the states of the internal detectors into the 8-bit serial shift register.
32
RSA
I
33
TSA
I
34 35 36 37 38 39 40 41 42 43
XMTA RTNA RTPA RDTA RDRA RDDA DGND VDDD CFLTA EN
O I I O O O -- -- I/O I
44
CLK
I
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Absolute Maximum Ratings (@ TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter 5 V Analog dc Supply 5 V Digital dc Supply Office Battery Supply Logic Input Voltage Logic Input Clamp Diode Current, per Pin Logic Output Voltage Logic Output Current, per Pin (excluding relay drivers) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Relative Humidity Range Ground Potential Difference (DGND to AGND) Symbol VDDA VDDD VBAT -- -- -- -- -- -- Tstg -- -- Min -0.5 -0.5 -65 -0.5 -- -0.5 -- -- -40 -40 5 +0.5 Value -- -- -- -- 20 -- 35 150 -- -- -- -- Max +7.0 +7.0 +0.5 VDDD + 0.5 -- VDDD + 0.5 -- -- +125 +125 95 -0.5 Unit V V V V mA V mA C C C % V
Notes: Analog and battery voltages are referenced to AGND; digital (logic) voltages are referenced to DGND. The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powering are (1) an inductor connected to Tip and Ring that can force an overvoltage on VBAT through external components if the VBAT connection chatters, and (2) inductance in the VBAT lead that could resonate with the VBAT filter capacitor to cause a destructive overvoltage.
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Electrical Characteristics
Generally, minimum and maximum values are testing requirements. However, some parameters may not be tested in production because they are guaranteed by design and device characterization. Typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum and maximum values apply across the entire temperature range (-40 C to +85 C) and entire battery range (-42 V to -58 V). Unless otherwise specified, typical values are defined as 25 C, VDDA = 5 V, VDDD = 5 V, VBAT = -48 V. Positive currents flow into the device. Table 2. Operating Conditions and Powering Parameter Temperature Range Humidity Range Supply Voltage: VDDA VDDD VBAT VDDA - VDDD Supply Currents (both channels active): IVDDA + IVDDD (5 V) IVBAT (-48 V)2 Supply Currents (both channels powerdown): IVDDA + IVDDD (5 V) IVBAT (-48 V)2 Total Power Dissipation (5 V; -48 V)3: Active (both channels) Powerdown (both channels) Power-supply Rejection4, 5 (50 mVrms ripple): Tip/Ring and XMT Thermal5: Thermal Resistance (still air) Operating Tjc -- -- Min -40 5 4.75 4.75 -42 -- -- -- -- -- -- -- Typ -- -- -- -- -48 -- -- -- -- -- -- -- Max 85 951 5.5 5.5 -58 0.5 19.0 -27.5 18.0 -2.0 1.40 185 Unit C %RH V V V V mA mA mA mA W mW
Refer to Figure 3. -- -- 47 155 C/W C
1. Not to exceed 26 grams of water per kilogram of dry air. 2. Includes VBAT current through the external dc feed resistors, assuming the loop is open. 3. Includes power dissipation in the external dc feed resistors per application diagram, assuming the loop is open. 4. VBAT power supply rejection depends on the battery noise cancellation circuit. The performance stated here applies only during the active state and assumes proper battery noise cancellation, i.e., a high-pass filter from VBAT to CBN and a resistor from RGBN to AGND which is 50 times the dc feed resistor connecting VBAT to Ring (refer to the application diagram). 5. This parameter is not tested in production. It is guaranteed by design and device characterization.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Electrical Characteristics (continued)
Table 3. Battery Feed, Switchhook Detectors (LCA and LCB), and Fault Detectors (FLTA and FLTB) Parameter Loop Resistance (3.17 dBm overload into 600 ) ILOOP = 18 mA at VBAT = -48 V Longitudinal Current Capability per Wire Switchhook Detector Loop Resistance2: Off-hook (LC = 1) On-hook (LC = 0) Fault Detector2, 3: |VTIP| or |VRING - VBAT| No Fault (FLT = 0) Fault (FLT = 1) Detection Delay tDET (no fault to fault; CFLT = 0.1 F) Release Delay (fault to no fault; CFLT = 0.1 F) Range1: Min Typ Max Unit mArms
1800 8.5 -- -- 4800
-- -- 4000 -- --
-- -- -- 3200 --
-- 39 10 1.6 tDET
36 36 -- --
33 -- 30 2.5 tDET
V V ms ms
1. Assumes 2 x 300 external dc feed resistors. 2. Detector values are independent of office battery and are valid over the entire range of VBAT. 3. Fault voltage is defined as the absolute value of the dc voltage across either dc feed resistor. If the voltage across either feed resistor exceeds this value, a fault is determined to be present. FLT is forced to a 0 when D2 = 1 (ringing state).
Table 4. Ring-Trip Detectors (RTA, RTB, RZA, and RZB) Parameter Ringing Frequency () dc Voltage ac Voltage Source1: 19 -39.5 60 2000 -- -- 3VBAT/4 -- 20 -- -- -- -- -- -- -- 28 -57 105 -- 200 80 -- VBAT/4 Hz V Vrms ms ms V V Min Typ Max Unit
Ring Trip2, 3 (RT = 1): Loop Resistance Trip Time ( = 20 Hz) RT Valid Ringing Source Zero Crossing (referenced to VBAT/2): Ringing Voltage Positive (RZ = 1) Ringing Voltage Negative (RZ = 0)
1. The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. 2. RT must also indicate ring-trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source. 3. Pretrip: Ringing must not be tripped by a 10 k resistor in parallel with an 8 F capacitor applied across Tip and Ring.
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Electrical Characteristics (continued)
Relay Drivers
The relay drivers operate using the VDDD supply. When VDDD is first applied to the device, the relay drivers must power up and remain in the off-state until the SLIC is configured via the serial data interface. The table below summarizes their parameter requirements. Table 5. Relay Drivers (RDRA, RDTA, RDRB, RDTB, RDDA, and RDDB) Parameter1 Off-state Output Current (VOUT = VDDD) On-state Output Voltage (IOUT = 40 mA) On-state Output Voltage (IOUT = 20 mA) Clamp Diode Reverse Current (VOUT = 0) Clamp Diode On Voltage (IOUT = 80 mA) Turn-on Time2 Turn-off Time2 Symbol IOFF VON VON IR VOC tON tOFF Min -- 0 0 -- VDDD + 0.5 -- -- Max 10 0.60 0.40 10 VDDD + 3.0 10 10 Unit A V V A V s s
1. Unless otherwise specified, all logic voltages are referenced to DGND. 2. This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 6. Analog Signal Pins Parameter PTA, PTB, PRA, and PRB: Surge Current (from external source): Continuous 1 ms Exponential Pulse (50 repetitions) 1 second, 60 Hz (60 repetitions) 10 s Rectangular Pulse (10 repetitions) Output Drive (PTA and PTB): Drive Current (sink only) Voltage Swing (IOUT = 15 mA) dc Bias Current (active state only) Output Drive (PRA and PRB): Drive Current (source only) Voltage Swing (IOUT = 15 mA) dc Bias Current (active state only) Output Impedance (60 Hz--3.4 kHz)1 Output Load Resistance (dc or ac)1 Min Typ Max Unit
-- -- -- -- 0.1 VBAT + 4 5.3 -15 VBAT -5.3 1 0
-- -- -- -- -- -- 5.6 -- -- -5.6 -- --
50 750 175 1.25 15 AGND 5.9 -0.1 AGND - 4 -5.9 -- 100
mAdc mA mArms A mA V mA mA V mA M k
1.This parameter is not tested in production. It is guaranteed by design and device characterization.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Electrical Characteristics (continued)
Relay Drivers (continued)
Table 6. Analog Signal Pins (continued) Parameter XMTA and XMTB: Output Drive Current Output Voltage Swing (3 mA load): Maximum Minimum Output Short-circuit Current2 Output Impedance (60 Hz--3.4 kHz) Output Load dc Resistance Output Load ac Impedance1 Output Load Capacitance1 VRNA and VRNB: Input Voltage Range Input Bias Current Input Impedance1 IRPA and IRPB: Input Offset Voltage (to respective VRN) Input Impedance CBNA and CBNB: Input Voltage Range Input Bias Current Input Impedance RGBNA and RGBNB: Input Offset Voltage (to respective CBN) Input Impedance TSA, TSB, RSA, and RSB: Surge Current (from external source) Input Voltage Range Input Bias Current Differential Input Impedance1 Common-mode Input Impedance1 External Capacitance (67 k source impedance)1 Min 3 VBAT VBAT + 10 -- -- 20 2 -- -1.75 -- 20 -- -- -1.75 -- 50 -- -- -- VBAT + 3 -- 50 50 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- VDDA +2.5 30 10 -- -- 50 3.5 1 -- 10 5 3.5 250 -- 10 5 25 AGND 1 -- -- 10 Unit mA V V mA k k pF V A M mV V nA M mV mAdc V A k M pF
1.This parameter is not tested in production. It is guaranteed by design and device characterization. 2.A VBAT or ground short on XMTA or XMTB will not cause a device failure.
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Electrical Characteristics (continued)
Transmission
Transmit direction is Tip/Ring to XMT. Receive direction is IRP/VRN to Tip/Ring. Table 7. Transmission Characteristics Parameter Longitudinal Balance (IEEE1 Std. 455--1976)2: 50 Hz--1 kHz 1 kHz--3 kHz Metallic to Longitudinal Balance2: 200 Hz--4 kHz RFI Rejection3: (0.5 Vrms, 50 source, 30% AM Mod. 1 kHz) 500 kHz--10 MHz 10 MHz--100 MHz Tip/Ring Signal Level ac Termination Impedance4 Total Harmonic Distortion (200 Hz--4 kHz)3 Transmit Gain ( = 1 kHz)5: Tip/Ring to XMT Receive Gain ( = 1 kHz): IRP Current to Differential Current Flowing from PT to PR VRV to IRP CBN Gain ( = 1 kHz): 1 RGBN Current to Current Flowing CBN to RGBN Gain vs. Frequency (transmit & receive; 1 kHz reference)3: 200 Hz--3.4 kHz Gain vs. Level (transmit & receive; 0 dBV reference)3: -50 dB to +3 dB Interchannel Crosstalk3: 200 Hz--3.4 kHz Idle-channel Noise (Tip/Ring; 600 termination): Psophometric3 C-message 3 kHz flat3 Idle-channel Noise (XMT; 600 termination): Psophometric3 C-message 3 kHz flat3 Min 54 50 30 Typ 70 66 -- Max -- -- -- Unit dB dB dB
-- -- -- -- -- -0.486 195 0.995 -49.5 0.995 -0.1 -0.05 -- -- -- -- -- -- --
-- -- -- 600 -- -0.500 200 1 -50 1 0 0 -- -- -- -- -- -- --
-65 -45 3.17 -- 0.3 -0.514 205 1.005 -50.5 1.005 0.1 0.05 77 -77 12 20 -77 12 20
dBV dBV dBm % -- -- -- -- -- dB dB dB dBmp dBrnC dBrn dBmp0 dBrnC0 dBrn0
1. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. 2. Assumes ideal external components. 3. This parameter is not tested in production. It is guaranteed by design and device characterization. 4. Transmission characteristics are specified assuming a 600 resistive termination; however, feedback using external components allows the user to adjust the termination impedance from the intrinsic 600 of the feed resistors to most ITU-T recommended complex termination impedances. 5. Measured with the L8575 SLIC connected per application diagram with ideal external components.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Electrical Characteristics (continued)
Serial Interface and Logic
The tables below summarize the parameter and timing requirements for logic inputs CLK, EN, DI, and DO. Table 8. Logic Inputs (CLK, EN, and DI) and Outputs (DO) Parameter1 High-level Input Voltage Low-level Input Voltage Input Bias Current (high and low) High-level Output Voltage (IOUT = -100 A) Low-level Output Voltage (IOUT = 180 A) Output Short-circuit Current (VOUT = VDDD) Output Load Capacitance2 Symbol VIH VIL IIN VOH VOL IOSS COL Min 2 0 -- VDDD - 1.5 0 1 0 Max VDDD 0.8 50 VDDD 0.4 35 50 Unit V V A V V mA pF
1. Unless otherwise specified, all logic voltages are referenced to DGND.
2.This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 9. Timing Requirements for CLK, EN, DI, and DO Parameter1 Input Rise and Fall Time, CLK & EN (10% to 90%)2 Maximum Input Capacitance2 Maximum CLK Frequency (50% duty cycle) Propagation Delay, CLK to DO2 Propagation Delay, EN to RD Outputs2 Minimum Setup Time from DI to CLK2 Minimum Setup Time from DI to EN2 Minimum Setup Time from EN to CLK2 Minimum Hold Time from CLK to DI2 Minimum Hold Time from EN to CLK2 Minimum Pulse Width of CLK Minimum Pulse Width of EN Symbol tR, tF CIN fMAX tPCO tPCR tSDC tSDE tSEC tHDC tHEC tWCK tWEN Min 0 -- -- 0 0 150 150 150 50 50 400 800 Max 70 5 1.25 350 10 -- -- -- -- -- -- -- Unit ns pF MHz ns s ns ns ns ns ns ns ns
1.Unless otherwise specified, all times are measured from the 50% point of logic transitions. 2.This parameter is not tested in production. It is guaranteed by design and device characterization.
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Electrical Characteristics (continued)
Serial Interface and Logic (continued)
0
-10
-20 PSRR (dB) VDDA (METALLIC) -30
-40 VBAT (METALLIC) -50
-60 101
102
103
104
105
106
FREQUENCY (Hz)
12-3307(F)
Figure 3. Power Supply Rejection vs. Frequency Diagram
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
The L8575 also includes:
s
Applications
General
The L8575 is a dual (channels A and B) subscriber line interface circuit (SLIC). Each channel operates independently such that no interaction occurs between the channels. The following description applies to both channels though the description may refer to only a single channel. Some circuits, such as reference circuits which do not impact interchannel crosstalk, are common to both channels. The L8575 device supplies a precise differential current to the Tip/Ring pair (via PT and PR) as a function of analog signal voltages on IRP and VRN. However, the current drivers connected to PT and PR are not designed to supply dc feed current to the loop. Two external resistors (typically 300 ), connected to office battery and ground, must be used in conjunction with the L8575 SLIC to provide dc loop current. These resistors will primarily determine the longitudinal balance of the line feed; thus, they must be matched appropriately to meet the longitudinal balance requirements (0.4% for 50 dB balance). These resistors also have a significant impact on the termination impedance of the SLIC. Feedback, using external components, allows the user to adjust the termination impedance from the intrinsic 600 of the feed resistors to most ITU-T recommended complex termination impedances. Since the L8575 does not supply dc to the loop, outputs PT and PR can be coupled to the Tip and Ring through a resistance high enough to allow for simple lightning protection of the drivers. However, the resistance must be low enough to achieve the coupling of sufficient ac signals to the Tip and Ring from the available power supply. Since the Tip and Ring drivers are current sources, the value of the resistance is arbitrary and does not affect the performance of the SLIC. A minimum value of 1400 (1.4 k) is required for protection purposes. The L8575 also senses the Tip voltage, Ring voltage, and differential Tip/Ring voltage via the TS and RS sense inputs. The differential dc voltage is used internally for switchhook detection. The Tip and Ring voltages are also used internally to detect faults on Tip and Ring. Both detector thresholds are preset internally. The status of each detector is monitored at pin DO by reading the 8-bit serial shift register. The differential Tip/Ring ac signal appears on analog output XMT.
Per-channel ring-trip detectors, loop closure detectors. Six relay drivers (three per channel). 8-bit serial-to-parallel and parallel-to-serial logic interface. Per-channel circuits which eliminate the battery noise that is coupled to the Tip and Ring through the dc feed resistors. Fault detection. Zero ring voltage detection.
s s
s
s s
Resistor Module
The L8575 requires certain external resistors at the Tip and Ring interface. Because of matching and protection requirements, one of the most economical options recommended to implement these registers is in a thick film resistor module. A schematic and a brief description of the function of each of these resistors is given in Figure 4. Note that Microelectronic Modules Corporation* MMC A31A8575AA Thick Film resistor module is an application-specific resistor module designed for use with the L8575 SLIC. The values, tolerance, matching, and power rating of the MMC A31A8575AA module are given in Table 10. Resistors R1 and R2 are the dc feed resistors. R1 is connected from battery to Ring, and R2 is connected from Tip to ground. The dc loop current is fed to the subscriber loop via these resistors. These resistors will set the dc I/V template of the line circuit with the I/V template being linear with a -1/600 slope. No constant current region at short dc loops is provided by resistors R1 and R2, or the L8575 SLIC.
* For additional information, contact Microelectronic Modules Corporation (MMC), 2601 S. Moorland Rd., New Berlin, WI 53151: U.S.A: (414) 785-6506 FAX Number: (414) 785-6516
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Applications (continued)
Resistor Module (continued)
FUSE RING RING 1 3 5 6 PR R6 R4 R8 GND 13 XMT 12 PT 14 R2 TIP 15 17 TIP 19 FUSE
R7 VBAT 7 R9 R3
R5
R1 Note:
RGBN 8
GND 9
RS 10
TS 11
5-3428(F)
Pin numbers are MMC A31A8575AA pin numbers. Resistors are labeled per MMC A31A8575AA description. Nodes are L8575 SLIC package nodes.
Figure 4. L8575 SLIC Resistor Module Table 10. MMC A31A8575AA Thick Film Resistor Module
Resistor R1 R2 R3 R4 R5 R6 R7 R8 R9 R9/R1 R1/R2 (R3 + R6)/(R4 + R5) Value 300 300 100 k 100 k 200 k 200 k 1.4 k 1.4 k 15 k 50 1 1 Tolerance 1.0% 1.0% 1.0% 1.0% 1.0% 1.0% 2.0% 2.0% -- 1.0% 0.35% 0.35% Power 2.0 W 2.0 W 250 mW 250 mW 250 mW 250 mW 0.5 W 0.5 W 10 mW -- -- -- Surge Rating Lightning: Power Cross Lightning: Power Cross None None Lightning: Power Cross Lightning: Power Cross Lightning: Power Cross Lightning: Power Cross None -- -- --
Note: For 50 dB longitudinal balance, 0.2% for 58 dB balances. Continuous power (rms).
Resistors R1 and R2 also provide a common-mode impedance of (300 || 300) 150 . These resistors will primarily determine the longitudinal balance of the line circuit; thus they must be matched appropriately to meet longitudinal balance requirements (0.35% for 50 dB and 0.2% for 58 dB). Also, they have a significant impact on the termination impedance of the SLIC. Feedback using external components (external components when a first- or second-generation codec is used) allows the user to set the termination impedance at 600 , or most ITU-T recommended complex termination impedances. Resistors R1 and R2, along with R3 and R7, are used in conjunction with the self-test feature of the L8575 SLIC. In this mode, the Ring current drive amplifier is saturated to ground, and the Tip amplifier is saturated to battery, which causes both the ring-trip and loop closure detectors to trip. Ring-trip and loop closure detector output are bits RT and LC, respectively, in the serial output stream. Lucent Technologies Inc.
Under normal operating conditions, resistors R1 and R2 will see the battery voltage less the Tip/Ring voltage. Assuming a Tip/Ring voltage of 6 V (representative of a short into a handset), the nominal continuous operating power of R1 and R2 is given by: (48 V - 6 V)2/600 = 2.94 W per R1 and R2 resistor pair 2.94 W/2 = 1.47 W per resistor The operating power rating of R1 and R2 is 2 W. This is the steady-state power rating of R1 and R2, and it is adequate for normal operating conditions. The ability of these resistors to withstand fault conditions depends on the power ratings of the individual resistors and on the power rating of the thick film resistor module itself. Obviously, the higher the power capabilities of the resistor module, the less susceptible the resistors are to damage during faults. The various fault conditions are discussed further in the Protection section of this data sheet. 17
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Hence, the operating power rating of 500 mW for R7 and R8. This is the nominal rating for R7 and R8 under normal operating conditions. Again, the ability of these resistors to withstand fault conditions depends on the power rating. Resistor R9 is also included on the thick film resistor module. This resistor is used to set the gain of the battery noise cancellation circuit. See the Battery Noise Cancellation section of this data sheet for design equations to set the value of R9.
Applications (continued)
Resistor Module (continued)
Resistors R3 through R6 set the gain of the SLIC in the transmit (2-wire to 4-wire) direction. This is shown in Figure 5.
R3 100 k
R5 200 k TIP R6 200 k RING R4 100 k
5-3422(F)
Protection
- XMT +
Because of the resistive feed architecture, a simple inexpensive protection scheme that does not require a separate external protection device may be used. The MMC A31A8575AA resistor module has specifications which are qualified to Bellcore GR-CORE-1089, UL*1459, UL 497A, FCC part 68.302 (d) & (e) and REA form 397G, ITU-T K20, and ITU-T K21. Lightning and power cross protection are provided by the two dc feed resistors, R1 and R2, in the external resistor module. Under fault conditions, these resistors serve as fault current-limiting resistors. Fault current is steered to ground and to battery via resistors R2 and R1, respectively. Thus, the battery design must be such that the various specified faults can be applied to the battery through 300 , without damaging the battery or the line circuit. Resistors R1 and R2 need to be designed to survive lightning surges and to dissipate power associated with a Ring ground dc fault and specified ac power cross faults--both a sneak under and full surge type fault. Under certain sustained fault conditions, R1 and R2 could fail when they are required to survive. For this reason, a per-channel fault detector is included on the L8575 SLIC. When the voltage across either R1 and/or R2 is greater than a nominal 36 V, the fault detect bit (FLT) in the serial data output will go high. The control logic on the line card detects FLT is high, and opens an external electromechanical relay (EMR) to isolate the resistors from the loop, enabling the resistors to service extended power cross. (Note the EMR is the test in or test out EMR, and this relay is driven by one of the internal relay drivers on the L8575 SLIC.) A delay of 10 ms to 30 ms is provided (using an external capacitor on pin CFLT) in the fault detector. This prevents transients on the Tip and Ring from tripping the fault detector when a fault is not present.
* UL is a registered trademark of Underwriters Laboratories, Inc.
Figure 5. L8575 SLIC Dual-Resistive Matching Requirements The matching of resistors R3 through R6 will determine the gain accuracy of the SLIC; therefore, these resistors must also be matched accordingly. The matching requirements are given in Table 10. Because of the high resistance values, the normal operating power of resistors R3 through R6 will be relatively low. Given design margin and thick film technology capabilities, a power rating of 250 mW for these resistors is not unreasonable. Resistors R7 and R8 are used to couple the PT and PR current drive amplifiers to Tip and Ring. Since the PT and PR drive amplifiers are current sources, the value of the series resistance does not affect the loop length or other performance of the SLIC, and may be arbitrarily high for protection purposes. A value of 1.4 k is adequate for protection purposes. Under normal operating conditions, these resistors will see the battery voltage less the Tip/Ring voltage. Assuming a Tip/Ring voltage of 6 V (representative of a short into a handset), the nominal continuous operating power of R7 and R8 is given by: (48 V - 6 V)2/2.8 k = 0.630 W per R7 and R8 resistor pair 630 mW/2 = 315 mW per resistor (R7 and R8) 18
Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Applications (continued)
Protection (continued)
The Tip/Ring drive amplifiers, which feed the ac signal to nodes PR and PT, are high-impedance current drivers. Since these nodes are current sources, the value of protection current-limiting series resistance does not affect the loop length or other SLIC performance, and may be arbitrarily high for protection purposes. Resistors R7 and R8 in the resistor module are used for this purpose. These resistors have a value of 1.4 k with a power rating 0.5 W. Internal diodes clamp nodes PR and PT to ground and battery. The voltage sense leads, RS and TS, are also exposed to the outside plant. Current to these nodes is limited by resistors R3 and R4 in the resistor module. Resistors R3 and R4 are 100 k, 250 mW resistors. Internal diodes also clamp nodes RS and TS to ground and battery. The ability of the resistors to survive faults is a function of the power dissipated in the individual resistors and the total power dissipated on the entire thick film module. Fault conditions include:
s
For example, a Ring ground fault assuming fault detector sneak under will result in a worst-case potential across the R1 of 39 V. The power dissipated in R1 under this condition is calculated as follows: (39 V * 39 V)/300 = 5 W Since this is a sneak under condition, the fault detector will not trigger and the time duration of the fault can be infinite. In the case of a longitudinally applied sneak under power cross, the maximum voltage seen, this time by both R1 (Ring) and R2 (Tip), is 39 Vp (voltage peak). The power dissipation is given by: Maximum Voltage = 39 Vp = 27.6 Vrms Maximum Power = (27.6 Vrms * 27.6 Vrms)/(300 ) = 2.54 W per resistor. Thus, 2.54 W will be dissipated per resistor or a total of 5.1 W in a longitudinal sneak under condition. If R1 and R2 are rated for 2 W, they can fail under these fault conditions. Also, the MMC A31A8575AA resistor module includes a fail-safe thermal fuse located at the Tip and Ring nodes (pin 1 and pin 19) of the module for this reason. A fail-safe fuse is recommended for any resistor module used with the L8575 SLIC. With thick film technology, not only is the power capabilities of the individual resistors important, but also the power handling capabilities of the entire module. The total module power dissipation is calculated by summing the power dissipation for each of the resistors under a given condition. For example, the module power dissipation for the above sneak under fault conditions is calculated in Table 11. Thus, the HIC will require a minimum power rating of 6 W continuous to survive these sneak under conditions.
A continuous worst-case (fault detector) sneak under condition of 39 Vdc applied metallically to Ring in the case of a Ring ground fault, and A sneak under condition of 39 Vp (voltage peak) applied to Tip and Ring, as described in Bellcore 1089, ITU-T K20, etc., in the case of power cross.
s
Additionally, there is a transient fault condition, assuming full specified power cross fault voltages (Bellcore 1089, ITU-T K20, etc.,) for a time duration equal to the maximum response time that it will take to isolate the line circuit from the fault via the fault detector and EMR described above. Table 11. Total Module Power Dissipation
Resistor (R) Value () Ring Ground Maximum dc Fault Voltage (V) 39 0 29 0 39 0 39 0 Ring Ground Maximum dc Fault Power (W) 5.07 0 0.015 0 0.0076 0 1.086 0 6.18
Longitudinal Fault Maximum Peak Voltage (Vp) 39 39 39 39 39 39 39 39 --
Longitudinal Fault Maximum rms Voltage (Vrms) 27.577 27.577 27.577 27.577 27.577 27.577 27.577 27.577 --
Longitudinal Fault Maximum rms Power (W) 2.535 2.535 0.0076 0.0076 0.0038 0.0038 0.543 0.543 6.18
1 300 2 300 3 100 k 4 100 k 5 200 k 6 200 k 7 1.4 k 8 1.4 k Total HIC Power:
Lucent Technologies Inc.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
The transmit interface uses an operational amplifier with four external resistors to perform a differential to single-ended conversion. Output XMT is referenced to ground (AGND). The longitudinal balance and gain accuracy at XMT depends on the matching of the external resistors. Because a large dc potential exists at XMT, a capacitor must be used to couple the ac signal to the low-voltage codec circuitry. The operational amplifier inputs are TS and RS. These inputs are also used by the fault-detection circuitry to detect fault voltages on Tip or Ring. A fault is detected when the magnitude of the voltage across either dc feed resistor exceeds a nominal 36 V (equivalent to approximately 4 W dissipation in either resistor). A delay is provided (using an external capacitor on pin CFLT) in the fault detector. This prevents transients on Tip and Ring from tripping the fault detector when a fault is not actually present.
Applications (continued)
Protection (continued)
Similar consideration to the individual resistor and total module power capability should be given to full voltage power faults, but taking into account the fault detector will isolate the SLIC and resistor module after some finite period of time. The fault detector indicates a fault in the serial data output stream in 10 ns to 30 ms. Recognition and relay activation time need to be considered.
Tip/Ring Drivers
Each channel of the L8575 utilizes a current source for the Tip/Ring driver. The driver is capable of sinking (but not sourcing) up to 15 mA from the Tip (PT) while swinging to within 4 V of office battery (VBAT), and sourcing (but not sinking) up to 15 mA to the Ring (PR) while swinging to within 4 V of ground (AGND). Since the current driver is not bidirectional, during transmission (powerup) each lead is biased at 5.6 mAdc.
Battery Noise Cancellation
The battery noise cancellation circuit senses the ac noise on the battery via the capacitor connected from input CBN to VBAT. It then couples this noise, 180 degrees out of phase, to the Ring current driver amplifier. This cancels the battery noise that is coupled to the Ring through the feed resistor connected to VBAT. Additionally, it ensures longitudinal balance which depends only on the matching of the battery feed resistors by creating an ac ground at VBAT with respect to signals on the Ring lead. For the cancellation to operate properly, both the phase and gain must be accurate. The battery noise cancellation gain is a transconductance that is equal to 50 divided by resistor R9 on the thick film resistor module connected from RGBN to ground (AGND). This value must be equal to the reciprocal of the dc feed resistor (1/300 ), that is, 1 50 ------ = --------------300 R9 R9 = 15 k It is advantageous if the two resistors are matched and tracked thermally, i.e., located on the same film integrated circuit (FIC).
Receive Interface
The receive interface circuitry couples the differential signal on receive inputs IRP and VRN to the Tip/Ring drivers. Input IRP is a low-impedance (<5 ) current input while VRN is a high-impedance voltage input. Internal feedback forces the voltage at IRP to be equal to VRN such that a voltage applied to VRN causes a current flow out of IRP, which equals that voltage divided by the impedance connected from IRP to AGND (assuming the input voltage is referenced to AGND). The receive interface and Tip/Ring drivers provide a current gain of 200, i.e., a differential output current flows from PT to PR which is 200 times the current flowing into IRP. The receive interface also provides a level shift since the inputs, IRP and VRN, are referenced to analog ground, while the outputs, PT and PR, swing between AGND and VBAT. The receive interface ensures that the input current is not converted to a common-mode current at PT and PR.
Transmit Interface
The transmit interface circuitry interfaces the differential voltage on Tip and Ring to transmit output XMT. The Tip/Ring differential voltage (both ac and dc) appears on output XMT with a gain of 0.5. 20 Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Applications (continued)
On-Hook Transmission
In powerup mode, the L8575 SLIC provides a dc bias of 5.6 mA. The 5.6 mA bias is also present under onhook conditions. The L8575 SLIC is able to support onhook transmission because of this bias. It is sufficiently high to drive a 3.17 dBm signal into a 600 or 900 loop under open-circuit conditions. An internal current source provides a dc bias of 112 A. There is an internal current gain of 50; thus (50 * 112 A) 5.6 mA flows from battery through R1 to PR, and 5.6 mA flows from PT through R2 to ground under on-hook conditions.
Serial Data Interface
A 4-wire serial interface (DI, DO, CLK, and EN) is used to pass data from the control logic on the line card to the L8575 SLIC, and to pass detector information from L8575 SLIC to the control logic on the line card. When enable input EN is high, data on input DI is clocked into an 8-bit shift register on a high-to-low transition of the clock input CLK. Eight latches (four per channel) are provided to store the data. Data is loaded into the eight latches from input DI and the first 7 bits of the shift register on the high-to-low transition of EN. When EN is low, a high-tolow transition on CLK loads all of the detector information (loop closure, fault zero voltage, and ring-trip from the internal detector circuitry) into the 8-bit shift register. When EN is high, data in the 8-bit shift register is clocked out on output DO on the high-to-low transition of CLK. Two latch outputs per channel drive relay drivers. The drivers are included on the L8575 SLIC. These are the relay drivers whose outputs are at external package nodes RDR (A&B) and RDT (A&B). The remaining two latch output power channels are internal control signals. These are logic data bits D0 (A&B) and D1 (A&B). These bits input to a combinational logic circuit that controls the operational state of each channel and also controls the state of the third relay driver. The third relay driver's output is at external package node RDD (A&B). Refer to the Truth Table (see Table 15) for more details. Note that up to 16 channels may be daisy-chained together. The DO lead of package 1 (channels 1 and 2) may be tied to the DI lead of package 2 (channels 3 and 4), etc. All EN and CLK should also be tied together in this mode. The L8575 SLIC device has an internal reset which guarantees that all relay drivers power up in the offstate when 5 V (VCCD and VCCA) is applied to the device. This reset operates properly only if input EN is held high (within 0.5 V of VCCD) when the 5 V is applied. An external pull-up resistor from the EN bus to VCCD satisfies this requirement, provided that the logicdriving EN does not pull the EN bus low during powerup.
Self-Test
The L8575 SLIC offers a self-test capability. This is set via logic inputs D1 and D0 in the serial input data stream. In this mode, shown in Figure 6, the Ring current drive amplifier is saturated to ground, and the Tip amplifier is saturated to battery, which causes both the ring-trip and loop closure detectors to indicate an offhook condition. In this operation mode, the ring relay must not be active. The ring relay driver output in the L8575 is at package nodes RDR (A&B). These relay drivers are controlled by logic inputs D2 (A&B) in the serial input data stream. See Table 14 for details.
200 k
100 k
300 k 200 k 100 k T 1.4 k R 1.4 k PTP 1.0 M 300 0.1 F 1.0 M VRING 8.25 M VBAT RTN PR PT
+ -
LCA/B
+ -
RTA/B
12-3423(F).r2
Figure 6. Self-Test Mode Circuit Lucent Technologies Inc. 21
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Applications (continued)
Serial Data Interface (continued)
Figure 7 shows the timing characteristics and requirement definitions.
DI tSDE tWEN EN tHDC tSDC CLK tPCO DO tSEC tHEC tWCK tWCK
12-3305(F).ar2
Figure 7. Timing Requirements for CLK, EN, DI, and DO Table 12. Truth Table for EN and CLK EN 1 0 CLK X Function Shift register clocked, QN = QN - 1; latches unaffected. Channel data latched into shift register; latches unaffected. Contents of shift register transferred to output latches.
Table 13. Output DATA Bit Definition DATA Bit D0A D1A D2A D3A D0B D1B D2B D3B Output D0A D1A RDRA RDTA D0B D1B RDRB RDTB Output Bit Definition Latch output state D0A (refer to Operating States section). Latch output state D1A (refer to Operating States section). Ringing relay driver A is on (RDRA low = relay energized) when D2A = 1. Test relay driver A is on (RDTA low = relay energized) when D3A = 1. Latch output state D0B (refer to Operating States section). Latch output state D1B (refer to Operating States section). Ringing relay driver B is on (RDRB low = relay energized) when D2B = 1. Test relay driver B is on (RDTB low = relay energized) when D3B = 1.
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Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Electrical Characteristics (continued)
Serial Data Interface (continued)
Table 14. Input DATA Bit Definition Input RZA FLTA RTA LCA RZB FLTB RTB LCB DATA Bit D0A D1A D2A D3A D0B D1B D2B D3B Input Bit Definition Channel A ringing voltage zero crossing detector output (positive = 1). Channel A fault detector output (loop fault = 1). Channel A ring-trip detector output (ring-trip = 1). Channel A switchhook detector output (off-hook = 1). Channel B ringing voltage zero crossing detector output (positive = 1). Channel B fault detector output (loop fault = 1). Channel B ring-trip detector output (ring-trip = 1). Channel B switchhook detector output (off-hook = 1).
FROM FROM INTERNAL INTERNAL RING VOLTAGE ZERO DETECT FAULT DETECT CIRCUIT CIRCUIT
FROM INTERNAL RING-TRIP CIRCUIT
FROM INTERNAL LOOP CLOSURE CIRCUIT
8-bit SHIFT RESISTOR
RZA
FLTA
RTA
LCA
RZB
FLTB
RTB
LCB
D0 DI D1 SEL Q
D0 D1 SEL Q
D0 D1 SEL Q
D0 D1 SEL Q
D0 D1 SEL Q
D0 D1 SEL Q
D0 D1 SEL Q
D0 D1 SEL Q DO
CLK
EN
DATA LATCHES
D Q QD0A
D Q QD1A
D Q QD2A
D Q QD3A
D Q QD0B
D Q QD1B
D Q QD2B
D Q QD3B
RELAY DRIVER
RELAY DRIVER
RELAY DRIVER
RELAY DRIVER
RELAY DRIVER
RELAY DRIVER
D0A
RDDA
D1A
RDRA
RDTA
D0B
RDDB
D1B
RDRB
RDTB
TO INTERNAL STATE CONTROL COMBINATIONAL LOGIC CIRCUITRY
INDICATES EXTERNAL PACKAGE MODE
12-3306(F).br3
Figure 8. Logic Diagram (Positive Logic; Flip-Flops Clocked on High-to-Low Transition) Lucent Technologies Inc. 23
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997 Powerdown State with Relay Driver RDD Operated
This is the disconnect state of the channel. It is the same as the powerdown state except that relay driver RDD is also operated. When required, this relay may be used to disconnect the external dc feed resistors in order to provide a high-impedance termination to the subscriber loop.
Operating States
Each channel of the L8575 has four operating states: active, test, powerdown with relay driver RDD ON, and powerdown with relay driver RDD OFF. These states are selected using 2 bits, D0 and D1, via the serial interface according to the truth table shown below. Table 15. Truth Table for D1 and D0 D1 1 1 0 0 D0 1 0 1 0 State Channel Active. Channel Test. Channel Powerdown and Relay RDD driver ON (RDD low). Channel Powerdown. Relay RDD driver OFF/RDD high.
Powerdown State
This is the normal idle state (scan state) of the channel. The loop-closure, ring-trip, and common-mode fault detectors are active, but all other circuits are shut down to conserve power. All circuits common to both channels remain active. The powerdown of channel A does not affect an active channel B and vice-versa.
Logic input D2 operates the ringing relay driver, RDR, independent of the state of bits D0 and D1; however, the ring-trip detector is enabled only when D2 operates the ringing relay driver. Hence, the ringing relay driver is not interchangeable with any of the other relay drivers. Logic input D3 operates the test relay driver, RDT, independent of the state of bits D0 and D2.
Ringing State (D2 = 1)
When D2 = 1, the ringing relay driver is activated. The operational state of the SLIC is unaffected except for the ring-trip and fault detectors. The digital portion of the ring-trip detector is enabled when D2 = 1 (relay drive activated) and disabled when D2 = 0 (relay drive deactivated). The ring-trip detector functions properly only when D2 = 1 so that a valid ringing signal (ac and dc) is present. When D2 = 0, the digital portion of the ring-trip detector is bypassed so that most of the ring-trip circuit can be tested in the test state. When D2 = 1, the fault detector is also disabled (FLT forced to 0).
Active State
This is the normal operating state (talk state) of the channel. All circuits are operational. The Tip drive current source sinks 5.6 mAdc from PT; the Ring drive current source sinks 5.6 mAdc into PR.
Test State
This is the test state of the channel. It is the same as the active state except that the Ring drive current source is saturated to ground and the Tip driver current source is saturated to VBAT. This forces the loop-closure and ring-trip detectors to indicate an off-hook. This state is valid only when the ringing relay is not operated (D2 = 0).
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Supervision
Off-Hook Detection
The off-hook detection threshold is a function of the dc feed resistors R1 and R2, and of a ratio of resistors that are fixed on the L8575 silicon die. Thus, when R1 = R2 = 300 , the off-hook threshold is set at 4 k. This relationship is shown in the equation below:
R1 + R2 RT = --------------------1 ------------ - 1 2 k
Ring-trip threshold (Figure 9) is calculated as follows: 300 RRF At ring-trip: VBAT -------------- = ------------------------------ V20 Hz (dc) ------------- RRTH RL + 600 2 If, VBAT = V20 Hz (dc) Then, 300 RRF ----------------- = ----------------------------2RRTH RL + 600
RRTH = RRF 1 + ------------------ 600 RL
RRF = 1 M; RL (ring-trip) = 6 k [Avg: 2 k & 10 k]
Where, RT is the loop closure threshold R1 = R2 = dc feed resistors = 300
RT1 K = -------------------------- = 0.4333 RT1 + RT2
RRTH = 11 M
2RRFCRF 100 ms
CRF = 0.047 F Ring-Trip Requirements
s
Where, RT1 and RT2 are internal resistors RT1 = 170 k RT2 = 130 k Thus, 300 + 300 RT = --------------------------------------------------------------- = 3900 4 k 1 ----------------------------------------------------- - 1 130 k 2 --------------------------------------------- 130 k + 170 k
Ringing signal: -- Voltage: minimum 35 Vrms, maximum 100 Vrms. -- Frequency: 17 Hz to 23 Hz. -- Crest factor: 1.4 to 2. Ringing trip: -- 100 ms (typical), 250 ms (VBAT = -33 V, loop length = 530 ). Pretrip: -- The circuits in Figure 10 will not cause ringing trip.
200 TIP RING SWITCH CLOSES < 12 ms 6 F
s
s
Ring-Trip Threshold
300 TIP LOOP RESISTANCE RL RING R1 TIP RTP 300 RRF RRTH VBAT VRTN (dc) = Z TIP
RRF
RING 10 k
CRF RTN 2 F 100 RING
12-2572 (C)
Figure 10. Ring-Trip Circuits
12-3424(F)
Figure 9. Ring-Trip Threshold
Lucent Technologies Inc.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Supervision (continued)
Fault Detection
The dc feed resistors R1 and R2 need to be designed to survive lightning surges and to dissipate power associated with a Ring ground dc fault and specified ac power cross faults--both in a sneak under and full surge type fault. Under certain sustained fault conditions, R1 and R2 could fail when they are required to survive. For this reason, a per-channel fault detector is included on the L8575. When the voltage across either R1 and R2 is a nominal 36 V (maximum 39 V), the fault detect bit, FLT in the serial data output, will go high, as calculated below: FLT = 1, if |VTIP| > 36 V nominal or |VRING - VBAT| > 36 V nominal, which corresponds to dc power in R1 or R2 > 4 W The control logic on the line card detects FLT is high and opens an external electromechanical relay to isolate the resistors from the loop, enabling the resistors to survive extended power cross. (Note the EMR is the test in or test out EMR, and this relay is driven by one of the internal relay drivers on the L8575 SLIC.) With an external 0.1 F capacitor on pin CFLT, a nofault to fault delay of 10 ns to 30 ms is provided in the fault detector. This prevents transients on Tip and Ring from tripping the fault detector when a fault is not present. There is a release delay (fault to no-fault) of 1.6 T to 2.5 T, where T is the no-fault to fault delay time.
Relay Drivers
Six relay drivers, three relay drivers per channel, are included on the L8575 SLIC. The output of these drivers are package nodes RDD (A&B), RDR (A&B), and RDT (A&B). Drivers RDR (A&B) are controlled by input bits D2 (A&B) on the serial input stream. Drivers RDT(A&B) are controlled by input bits D3 (A&B) on the serial input stream. In these cases, a logic 1 on D2 or D3 activates the respective relay driver. Relay drivers RDD (A&B) are controlled per the truth table (see Table 2) via bits D0 (A&B) and D1 (A&B). In order to activate driver DDR, D0 = logic 1 and D1 = logic 0. Note that with D0 = logic 1 and D1 = logic 0, the SLIC is set to the channel powerdown state. Relay drivers RDR (A&B) must be used for the Ring relay function because the ring-trip detector is enabled only when D2 is high; that is, when D2 operates the ringing relay driver (RDR). Hence, the test and ringing relay drivers are not interchangeable. When relay driver RDD is active, the L8575 is forced into a powerdown state. Thus, using RDD with the testin relay is not appropriate. This relay may be used for test out or as a channel isolation relay. Relay driver RDT is controlled by D3 in the serial bit stream. Logic input D3 operates driver RDT independent of the state of bits D0, D1, and D2. RDT may be used with a test-in, test-out, or channel isolation relay.
Zero Voltage Current Cross
The L8575 provides a bit, RZA (and RZB for channel B), in the serial data stream which gives an indication when the ringing voltage is crossing zero. This signal bit may be used in timing the application and removal of the ringing signal.
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
dc Characteristics
I/V Characteristics
Resistors R1 and R2 are the dc feed resistors. R1 is connected from battery to Ring, and R2 is connected from Tip to ground. The dc loop current is fed to the subscriber loop via these resistors. These resistors will set the dc I/V template for the line circuit, with the I/V template being linear with a -1/600 slope. No constant current region at short dc loops is provided by resistors R1 and R2 or the L8575 SLIC. The dc Tip/Ring voltage under open loop conditions is 3.36 V less than battery. In order to drive an on-hook ac signal, the Tip and Ring voltage must be set to a value less than the battery voltage. The amount that the open loop voltage (VOC) is decreased relative to the battery (VBAT) is referred to as the overhead voltage (VOH). This overhead voltage is due to 5.6 mA of bias current flow from both the Tip and Ring current drive amplifier's flow through resistors R2 and R1, respectively. Thus, the overhead is given by: VOH = (R1 x 5.6 mA) + (R2 x 5.6 mA) VOH = (300 x 5.6 mA) + (300 x 5.6 mA) = 3.36 V The nominal dc I/V template for the L8575 SLIC is shown in Figure 11.
80 70 60
Loop Length
The loop range equation is given by:
VBAT - VOH RL = ---------------------------------- - R1 - R2 IL
Where, RL is the dc resistance of the subscriber loop. IL is the dc loop current. |VBAT| is the magnitude of the battery voltage. VOH is the overhead voltage--nominal 3.36 V. R1 = R2 = dc feed resistors = 300 . Thus, for a nominal -48 V battery with a minimum 18 mA loop requirement, the loop range will be:
48 V - 3.36 V RL = -------------------------------------- - 300 - 300 0.018 A
RL = 1880
ILOOP (mA)
50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 50
VT-R (V)
VOC (44.7)
VBAT (48)
12-3430(F).r1
Figure 11. L8575 SLIC I/V Template
Lucent Technologies Inc.
27
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Second-Generation Codecs This class of devices includes a microprocessor interface for software control of the gains and hybrid balance. The hybrid balance is included in the device. ac programmability adds application flexibility and saves several passive components. It also adds several I/O latches that are needed in the application. It does not have the transmit op amp, since the transmit gain and hybrid balance are set internally. Third-Generation Codecs This class of devices includes the gains, termination impedance, and hybrid balance--all under microprocessor control. Depending on the device, it may or may not include latches. In the codec selection, increasing software control and flexibility are traded for device cost. To help decide, it may be useful to consider the following:
s
ac Design
Codec Features and Selection Summary
There are four key ac design parameters:
s
Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway. Receive gain is done from the PCM highway to the transmit port. Hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port.
s
s
s
At this point in the design, the codec needs to be selected. The discrete network between the SLIC and the codec can then be designed. Below is a brief codec feature and selection summary. First-Generation Codecs These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, and -law/A-law selectability. This generation of codec has the lowest cost. It is most suitable for applications with fixed gains, termination impedance, and hybrid balance.
Will the application require only one value for each gain and impedance? Will the board be used in different countries with different requirements? Will several versions of the board be built? If so, will one version of the board be most of the production volume? Does the application need only real termination impedance? Does the hybrid balance need to be adjusted in the field?
s
s
s
s
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
ac Design (continued)
Design Equations
The following section gives the relevant design equations to choose component values for any desired gain, termination and balance network, assuming a complex termination is desired. Complex termination will be specified in one of the two forms shown below:
R2 R1 C R1 R2 C
Define the gain constant, K, as follows:
KRCV = K010 KTX = ------10 K0
Rx/20
for receive gain
1
Tx/20
for transmit gain
Where, RX = desired receive (or PCM to Tip/Ring) gain in dB TX = desired transmit (or Tip/Ring to PCM) gain in dB
K0 = ZT 1 kHz ------------------------- = power transfer ratio 600
(SERIES FORM)
(PARALLEL FORM)
12-3425(F)
|ZT| 1 kHz is the magnitude of the complex termination impedance ZT being synthesized, calculated at 1000 Hz. This equation assumes that the TLP of the codec is 0 dBm referenced to 600 . The following equation applies when referring to Figure 13:
C R1R2 + R1 + R2 - jR2 C ZT = -------------------------------------------------------------------------------------22 2 1 + R2 C
2 2 2 2
Figure 12. Equivalent Complex Terminations Both forms are equivalent to each other, and it does not matter which form is specified. The component values in the interface circuit of Figure 12 are calculated assuming the parallel form is specified. If the termination impedance to be synthesized is specified in the series form, convert it to the parallel form using the equations below:
R1 = R1 + R2 R1 + R2R1 R2 = -----------------------------R2 C C = -----------------------------------------R1 R1 2 1 + 2 ------ + ------ R2 R2
2
Where, = 2 = 1000 Hz CR1R2 is defined per Figure 12 (series form), and
ZT = 2 C 2 R1R2 2 + R1 + R2 R2 2 C ----------------------------------------------------------- + ---------------------------------- 22 2 1 + 2 R2 2 C 2 1 + R2 C
2 2
Note that if the termination impedance is specified as pure resistive: R2 = R2 = 0 and C = C =
Lucent Technologies Inc.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
ac Design (continued)
Design Equations (continued)
RGX RESISTOR MODULE 100 k GSX TS - AX + 1/2 L8575 VRN VRN
RGX1
VFXIN
- +
200 k 200 k R2 R1 + Z T/R VT/R IT/R - C1
100 k
RS
RT1 VBAT 300 PT 1.4 k PR 1.4 k 300 IRP LRP RECEIVE INTERFACE RT2 CT ZIRP CR RRV1 XMT VXMT RHB1
+2.4 V
RRV2
VFRO
1/4 T7504 CODEC
VBAT
12-3429.C (F)
Figure 13. Initial ac Interface for Complex Termination Between L8575 SLIC and T7504 Codec Note: dc Blocking Capacitors (CB) Not Shown, CT and CR Separate
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
The 300 feed resistors contribute 600 to the termination impedance. The termination impedance associated with the circuit in Figure 13 consists of this inherent 600 feeding impedance in parallel with:
s
ac Design (continued)
Design Equations (continued)
The Tip/Ring differential current is given by: VRN IT/R = 200 IRP - ---------- ZIRP The voltage at pin XMT is given by: - VT/R VXMT = ------------2 The component values in the ac interface of Figure 13 are calculated (for the transmit and receive gains defined by the respective gain constants KRX and KRCV, and for the termination impedance seen in Figure 12) using the following equations: 100R1 RRV1 = -----------------KRCV 100R2 RRV2 = -----------------KRCV KRCVC CR = ------------------100 RRV1 1 RGX1 1 ----------------------------- = ------------ --------- - -------- RGX1 + RT1 100 600 R1 600 = 2 x 300 feed resistors RGX = 2 x KTX(RGX1 + RT1) 100R1 RGX1 C CT = --------- 1 + ------------ 1 + ------------------ 100 RT1 RRV1 R2C RT2 = -------------CT
A negative impedance, where, 2 RGX1 --------- x ----------------------------100 RGX1 + RT1
s
A positive impedance, where, 1 RT2 + ------------- x RGX1 + RT1 ----------------------------- jCT RT1
The negative and positive impedance terms are used to adjust the termination impedance from the inherent 600 to any complex termination. Note in the case of a pure 600 dc termination, the two 300 feed resistors provide this termination, and components RT1, RT2, and CT are not used in the ac interface circuit. Using the circuit of Figure 13, the ratio of capacitors CT and CR will affect the (transmit and receive) gain flatness, and to a lesser degree the return loss of the line circuit. Thus, depending on the requirements, CT and CR may need to be tight tolerance capacitors. If this is the case, capacitors CT and CR may be combined into a single capacitor with a looser tolerance. This is illustrated in Figure 14.
XMT
XMT
RT2
-- -- --
RT2
CT IRP CR RRV2 VFRO IRP CS = CT + CR RRV2 VFRO
RRV1 RRV1
12-3426a(F)
Figure 14. Revised ac Interface CT and CR Combined into a Single Capacitor CS Lucent Technologies Inc. 31
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
With a -48 V battery, the dc voltage at node XMT will ( VTIP - VRING ) be a nominal -22 V or ---------------------------------------- - 4 V. This is the 2 common-mode dc voltage. This will cause a dc current flow from the codec to the SLIC. This current will not affect ac performance, but it will effectively waste power. To avoid this wasted power consumption, blocking capacitors can be added. The blocking capacitors block the dc path from any low impedance node at the codec to SLIC node XMT. Blocking capacitors are added to the application diagram in Figure 16. After the blocking capacitor CB is added, the above component values may have to be adjusted slightly to optimize performance.
RT2
ac Design (continued)
Design Equations (continued)
To scale CS (higher), increase CT (and decrease RT2) by increasing the RGX1/ (RGX1 + RT1) ratio by rearranging the circuit in Figure 13 and by adding resistor RSC from XMT to IRP as shown in the figure below:
VRN RGX1 RT1 CB XMT RSC CT IRP
12-3427a(F)
The effects of the blocking capacitor are best evaluated and optimized by circuit simulation. Contact your Lucent Technologies Microelectronics Group Account Representative for information on availability of a PSPICE* model. Figure 16 shows a complete reference design using the L8575 SLIC and T8502/3 codec. This line circuit is designed to meet the requirements of the People's Republic of China. The basic ac design parameters are listed below: Termination impedance: 200 + 680 || 0.1 F Hybrid balance network: 200 + 680 || 0.1 F Transmit gain: 0 dB Receive gain: -3.5 dB or -7.0 dB Notice that the interface circuit between the L8575 and T8502/3 is designed for a receive gain of -3.5 dB. The T8502 codec offers a pin selectable receive gain of 0 dB or -3.5 dB. Thus, via logic control, a receive gain of either -3.5 dB or 7.0 dB is achieved. The T8502/3 codec is a dual +5 V only codec. When used with the dual L8575 SLIC, a complete low-cost, dual-line circuit is achieved.
*PSPICE is a registered trademark of MicroSim Corporation.
Figure 15. Addition of Resistor RSC from XMT to IRP Then,
( RRV1 || RSC ) 1 RGX1 RRV1 1 - ----------------------------- = ------------------------------------ --------- - -------- + -----------------------------100 RGX1 + RT1 600 R1 RRV1 + RSC
Once the gains and complex termination are set, if the hybrid balance network is identical to the termination impedance, then the hybrid balance is set by a single resistor (shown in Figure 15) and is computed as follows: RGX RHB = -------------------------------KRCV x K TX The L8575 SLIC is ground referenced. However, a +5 V only codec, such as T7504, is referenced to +2.5 V. The L8575 SLIC has sufficient dynamic range to accommodate an ac signal from the codec that is referenced to +2.5 V without clipping distortion.
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Application Diagram
The following diagram and table show the basic components required with the L8575 SLIC. Specific component values are given in cases where the value is fixed. In cases where the value may change (i.e., components that determine the ac interface), the value is not listed but equations to determine these values are given later in this document. Table 16. External Components Required Comp. R1 R2 R3 R4 R5 R6 R7 R8 R9 CVCC CVDD CBAT RCBN CCBN CRF RRF1 RRF2 RRTH CFLTA CB1 CB2 RT1 RT2 RGX RGX1 RRV1 RRV2 C2 or CS RHB1 Function dc Feed Protection dc Feed Protection Transmit Gain Transmit Gain Transmit Gain Transmit Gain Protection Protection Battery Noise Cancellation VCC Filter VDD Filter VBAT Filter Battery Noise Cancellation Battery Noise Cancellation Ring Trip Ring Trip Ring Trip Ring Trip Threshold Fault Filter dc Blocking dc Blocking ac Interface ac Interface ac Interface ac Interface ac Interface ac Interface ac Interface ac Interface Implementation Resistor Module Resistor Module Resistor Module Resistor Module Resistor Module Resistor Module Resistor Module Resistor Module Resistor Module External External External External External External External External External External External External External External External External External External External External Value 300 300 100 k 100 k 200 k 200 k 1.4 k 1.4 k 15 k 0.1 F 0.1 F 0.1 F 301 k 0.1 F 0.1 F 1 M 1 M 11 M 0.1 F 0.1 F 0.1 F 34 k 7.32 k 150 k 52.3 k 113 k 35.7 k 2.7 nF 221 k Attribute* 1.0%, 2 W 1.0%, 2 W 1.0%, 25 mW 1.0%, 25 mW 1.0%, 25 mW 1.0%, 25 mW 2.0%, 0.1 W 2.0%, 0.1 W 10 mW 20%, 10 V 20%, 10 V 20%, 100 V 1%, 1/16 W 20%, 100 V 20%, 100 V 20%, 100 V 1%, 1/16 W 1%, 1/16 W 20%, 100 V 20%, 50 V 20%, 50 V 1%, 1/32 W 1%, 1/32 W 1%, 1/32 W 1%, 1/32 W 1%, 1/32 W 1%, 1/32 W 5%, 10 V 1%, 1/32 W
* Power is continuous RMS power. R1/R2 = 1, with a tolerance of 0.35% for 50 dB longitudinal balance, 0.2% for 58 dB longitudinal balance. Fuses on F1 and F2 provide fail-safe operation if excessive overvoltage conditions exist on Tip and Ring. They will not operate if the total power dissipation of the entire resistor network is >5.0 W at 85 C. (R3 x R6)/(R4 x R5) = 1 with a tolerance of 0. 35% for 50 dB longitudinal balance, 0.2% for 58 dB longitudinal balance. R9/R1 = 100 with a tolerance of 0.5%.
Lucent Technologies Inc.
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L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Application Diagram (continued)
+5 D 0.1 F CVDD
5, 41 VDDD DGND PTA DI 33 TSA DO CLK 3 2 44 43 6, 40
KTA 300 R2
37
KTA
38 RDRA
KTA
30 RDDA
KTB
7 RDDB
KTB
8 RDRB
KTB
9 RDTB
1.4 k R8 200 k R6
RDTA 28
DG SERIAL INTERFACE BUSES TO CONTROL LOGIC CFLTA 0.1 F THICK FILM RESISTOR MODULE
TIP KTA2
100 k R4 XMTA (CHANNEL A) TEST OUT BUS 100 k R3 KTA1 200 k R5
34 XMTA
EN
CFLTA
42
RGBNA
31
15 k R9 RGX 150 k
GSX(n) 1/2 T8502/3 CODEC VFXIN(n)
L8575
32 VRNA RSA 30
RING
1.4 k KRA2 R7 THICK FILM RESISTOR MODULE 300 R1 1 M RF1 0.1 F 1 M KRA1 VRNG (RINGING SUPPLY) RF2 11 M RRTH
34 k RT1
52.3 k RGX1 0.1 F RHB2 221 k
27
PRA
36
RTPA IRPA 29
CRF
35 RTNA
CB1 XMTA 113 k RRV1 2.7 nF CS = CT + CR CB2 RRV2 35.7 k 0.1 F XMTA
VFRO(n) GS
GAIN SELECT
VBAT
18 13 12
PTB TSB XMTB RSB PRB RTPB RTNB CBNA 24 CBNB 22 VBAT 21, 25 AGND 20, 26 VDDA 23 CFLTB RGBNB VRNB IRPB 4 15 16 17
RT2 7.32 k TERMINATION/HYBRID 200 + 680 II 0.1 F TX = 0 dB RX = -3.5 dB/-7.0 dB SAME AS CHANNEL A
SAME AS CHANNEL A
14 19 10 11
0.1 F 0.1 F CVCC +5 A
12-3308(F).a
0.1 F 301 k RCBN CCBN
CBAT VBAT (OFFICE BATTERY)
Figure 16. Typical Application Diagram with Blocking Capacitors (CB) Included
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Lucent Technologies Inc.
Advance Data Sheet March 1997
L8575 Dual-Resistive, Low-Cost SLIC
Outline Diagram
44-Pin PLCC
Dimensions are in millimeters.
17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE
6
1
40
7
39
16.66 MAX 17.65 MAX
17
29
18
28
4.57 MAX SEATING PLANE 1.27 TYP 0.53 MAX 0.51 MIN TYP 0.10
5-2506r7
Lucent Technologies Inc.
35
L8575 Dual-Resistive, Low-Cost SLIC
Advance Data Sheet March 1997
Ordering Information
Device Part No. LUCL8575 BP LUCL8575 BP-TR Description Dual-Resistive SLIC Dual-Resistive SLIC Package 44-pin PLCC 44-pin PLCC (Tape & Reel) Comcode 107890386 107890394
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1997 Lucent Technologies Inc. All Rights Reserved
March 1997 DS97-140ALC (Replaces DS96-099LCAS)
Printed On Recycled Paper

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